notes/education/computer engineering/ECE2700/Verilog.md

## Boolean Engineering
- Truth tables
	- Only practical for small circuits
- Schematic capture
	- Using CAD to place logic gates on a virtual canvas
	- Facilitates *hierarchical design*
	- Good for larger circuits
	- Don't scale well for very large circuits
- Hardware Description Languages
	- Enables hierarchical design
	- Standardized by IEEE
	- Design is more portable
	- Usable in combination with schematic design

# Verilog
- Originally developed by Gateway Design Automation
- Put in public domain in 1990
- Standardized in 1995
- Originally intended for simulation of logic networks, later adapted to synthesis

- Behavioral Verilog describes broader behavior, at a higher level
```verilog
//              V---V---v--v-----portlist (not ordered)
module example1(x1, x2, s, f);
	// Defining the types of the various ports
	input x1, x2, s;
	output f;
	// The first argument is the output value.
	// In this example, `k`, `g`, `h`, `f` are implicitly declared.
	// They could also be declared manually with the syntax `wire foo`, alongside the `input` and `output` declarations
	not(k, s); // You can also NOT a variable using a tilde, eg `~s`
	and(g, k, x1);
	and(h, s, x2);
	or(f, g, h);
endmodule	
```

```verilog
//              V---V---v--v-----portlist (not ordered)
module example1(x1, x2, s, f);
	// Defining the types of the various ports
	input x1, x2, s;
	output f;
	// You can also do this
	assign f = (~s & x1) | (s & x2);
	// Or this
	always @(a, b)
	// always @(....) says "do this stuff whenever any of the values inside of @(...) change"
		{s1, s0} = a + b;
endmodule	
```
- Structural Verilog describes how things are laid out at a logic level

## Testbench Layout
- Define UUT module
- Initialize Inputs
- Wait
- Test every possible combination of inputs and validate that the outputs are correct
- Debug output can be displayed with `$display("Hello world");`