vault backup: 2025-01-27 10:37:59
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- Standardized in 1995
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- Originally intended for simulation of logic networks, later adapted to synthesis
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- Behavioral Verilog describes broader behavior, at a higher level
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```verilog
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// V---V---v--v-----portlist (not ordered)
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module example1(x1, x2, s, f);
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@ -34,6 +35,23 @@ module example1(x1, x2, s, f);
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endmodule
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```
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- Behavioral Verilog describes broader behavior, at a higher level
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```verilog
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// V---V---v--v-----portlist (not ordered)
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module example1(x1, x2, s, f);
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// Defining the types of the various ports
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input x1, x2, s;
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output f;
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// You can also do this
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assign f = (~s & x1) | (s & x2);
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// Or this
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always @(a, b)
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// always @(....) says "do this stuff whenever any of the values inside of @(...) change"
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{s1, s0} = a + b;
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endmodule
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```
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- Structural Verilog describes how things are laid out at a logic level
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## Testbench Layout
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