vault backup: 2025-01-17 14:58:02

education/computer engineering/ECE2700/Verilog.md

@@ -0,0 +1,15 @@
+## Boolean Engineering
+- Truth tables
+	- Only practical for small circuits
+- Schematic capture
+	- Using CAD to place logic gates on a virtual canvas
+	- Facilitates *hierarchical design*
+	- Good for larger circuits
+	- Don't scale well for very large circuits
+- Hardware Description Languages
+	- Enables hierarchical design
+	- Standardized by IEEE
+	- Design is more portable
+	- Usable in combination with schematic design
+
+# Verilog

education/math/MATH1050/Systems of Equations.md

@@ -4,6 +4,7 @@
 | Inconsistent | Parallel lines, no solution                                                                                            |
 | Independent  | The lines only cross at one point.                                                                                     |
 | Dependant    | The lines are identical, and there are infinitely many solutions. Both equations represent the same line when plotted. |
+
 # Solving
 ## Graphing
 Graph the two equations, and look for points where they intersect