vault backup: 2025-01-17 15:56:27

2025-01-17 15:56:27 -07:00
parent 77ec466cd0
commit 589b03582b
1 changed files with 4 additions and 3 deletions
--- a/engineering/ECE2700/Verilog.md
+++ b/engineering/ECE2700/Verilog.md
@@ -19,6 +19,7 @@
 - Originally intended for simulation of logic networks, later adapted to synthesis

 ```verilog
+//              
 module example1(x1, x2, s, f);
 	input x1, x2, s;
 	output f;
@@ -27,6 +28,6 @@ module example1(x1, x2, s, f);
 	and(g, k, x1);
 	and(h, s, x2);
 	or(f, g, h);
-endmodule
-	
-```
+endmodule	
+```
+