vault backup: 2025-01-27 10:47:59

2025-01-27 10:47:59 -07:00 · 2025-01-27 10:47:59 -07:00 · 46f7a2c9b5
commit 46f7a2c9b5
parent 0acfe2ddd3
1 changed files with 1 additions and 4 deletions
--- a/engineering/ECE2700/Verilog.md
+++ b/engineering/ECE2700/Verilog.md
@ -56,7 +56,4 @@ endmodule
 - Initialize Inputs
 - Wait
 - Test every possible combination of inputs and validate that the outputs are correct
-
- $\$display("Hello, world)$ 
-
-
+- Debug output can be displayed with `$display("Hello world");`