vault backup: 2025-01-17 16:01:27

education/computer engineering/ECE2700/Verilog.md

@@ -19,11 +19,14 @@
 - Originally intended for simulation of logic networks, later adapted to synthesis
 
 ```verilog
-//              
+//              V---V---v--v-----portlist (not ordered)
 module example1(x1, x2, s, f);
+	// Defining the types of the various ports
 	input x1, x2, s;
 	output f;
-
+	// The first argument is the output value.
+	// In this example, `k`, `g`, `h`, `f` are implicitly declared.
+	// They could also be declared manually with the syntax `wire foo`, alongside the `input` and `output` declarations
 	not(k, s);
 	and(g, k, x1);
 	and(h, s, x2);