vault backup: 2025-02-03 11:29:24

2025-02-03 11:29:24 -07:00
parent 70f2be9fcb
commit 1e688a3614
1 changed files with 3 additions and 1 deletions
--- a/engineering/ECE2700/Verilog/Modules.md
+++ b/engineering/ECE2700/Verilog/Modules.md
@ -84,3 +84,5 @@ module test(a, b, c);
 	// -------- snip ---------
 endmodule
 ```
+
+# Instantiation