From 1e688a361406488695a2defa00d08c2f15aa11db Mon Sep 17 00:00:00 2001 From: arc Date: Mon, 3 Feb 2025 11:29:24 -0700 Subject: [PATCH] vault backup: 2025-02-03 11:29:24 --- education/computer engineering/ECE2700/Verilog/Modules.md | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/education/computer engineering/ECE2700/Verilog/Modules.md b/education/computer engineering/ECE2700/Verilog/Modules.md index c02a620..ea7c1bf 100644 --- a/education/computer engineering/ECE2700/Verilog/Modules.md +++ b/education/computer engineering/ECE2700/Verilog/Modules.md @@ -83,4 +83,6 @@ module test(a, b, c); output [7:0] c; // -------- snip --------- endmodule -``` \ No newline at end of file +``` + +# Instantiation