diff --git a/education/computer engineering/ECE2700/Verilog/Modules.md b/education/computer engineering/ECE2700/Verilog/Modules.md
index c02a620..ea7c1bf 100644
--- a/education/computer engineering/ECE2700/Verilog/Modules.md	
+++ b/education/computer engineering/ECE2700/Verilog/Modules.md	
@@ -83,4 +83,6 @@ module test(a, b, c);
 	output [7:0] c;
 	// -------- snip ---------
 endmodule
-```
\ No newline at end of file
+```
+
+# Instantiation