vault backup: 2025-02-03 11:24:08

education/computer engineering/ECE2700/Verilog/Modules.md

@@ -37,7 +37,7 @@ There are 3 kinds of ports:
 - `output`: Output ports can be written to, but not read from.
 - `inout`: Inout ports can send *and* receive values.
 
-Ports can be declared in the port list, or in the module body. Ports declared in the port list can optionally omit their type, to be specified within the body of the module:
+Ports can be declared in the port list, or in the module body. Ports declared in the port list can optionally omit their type and only declare a name, to be specified within the body of the module:
 ```verilog
 module half_adder(
 	a,
@@ -49,6 +49,24 @@ module half_adder(
 	input b;
 	output sum_bit;
 	output carry_bit;
+	// ----------- snip -----------
+endmodule
+```
+
+The full type of a port can also be defined within the portlist:
+```verilog
+```verilog
+module half_adder(
+	input wire a,
+	input wire b,
+	output wire sum_bit,
+	output wire carry_bit
+	);
+	input a;
+	input b;
+	output sum_bit;
+	output carry_bit;
+	// ----------- snip -----------
 endmodule
 ```
 
@@ -60,6 +78,9 @@ If no type is defined, ports are implicitly defined as *nets* of type `wire`.
 Ports can be a vector type:
 ```verilog
 module test(a, b, c);
-		
+	input [7:0] a;
+	input [7:0] b;
+	output [7:0] c;
+	// -------- snip ---------
 endmodule
 ```