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2025-01-17 15:56:27 -07:00 · 2025-01-17 15:56:27 -07:00 · 589b03582b
commit 589b03582b
parent 77ec466cd0
1 changed files with 4 additions and 3 deletions
--- a/engineering/ECE2700/Verilog.md
+++ b/engineering/ECE2700/Verilog.md
@ -19,6 +19,7 @@
 - Originally intended for simulation of logic networks, later adapted to synthesis

 ```verilog
+//              
 module example1(x1, x2, s, f);
 	input x1, x2, s;
 	output f;
@ -28,5 +29,5 @@ module example1(x1, x2, s, f);
 	and(h, s, x2);
 	or(f, g, h);
 endmodule	
-	
 ```
+