notes/education/computer engineering/ECE2700/Verilog.md

Boolean Engineering

• Truth tables
  • Only practical for small circuits
• Schematic capture
  • Using CAD to place logic gates on a virtual canvas
  • Facilitates hierarchical design
  • Good for larger circuits
  • Don't scale well for very large circuits
• Hardware Description Languages
  • Enables hierarchical design
  • Standardized by IEEE
  • Design is more portable
  • Usable in combination with schematic design

Verilog

• Originally developed by Gateway Design Automation
• Put in public domain in 1990
• Standardized in 1995
• Originally intended for simulation of logic networks, later adapted to synthesis

//              
module example1(x1, x2, s, f);
	input x1, x2, s;
	output f;

	not(k, s);
	and(g, k, x1);
	and(h, s, x2);
	or(f, g, h);
endmodule