From 589b03582b94415ce826bb64c170994c058cd8d0 Mon Sep 17 00:00:00 2001
From: arc <zleyyij@users.noreply.github.com>
Date: Fri, 17 Jan 2025 15:56:27 -0700
Subject: [PATCH] vault backup: 2025-01-17 15:56:27

---
 education/computer engineering/ECE2700/Verilog.md | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/education/computer engineering/ECE2700/Verilog.md b/education/computer engineering/ECE2700/Verilog.md
index f356e82..11089df 100644
--- a/education/computer engineering/ECE2700/Verilog.md	
+++ b/education/computer engineering/ECE2700/Verilog.md	
@@ -19,6 +19,7 @@
 - Originally intended for simulation of logic networks, later adapted to synthesis
 
 ```verilog
+//              
 module example1(x1, x2, s, f);
 	input x1, x2, s;
 	output f;
@@ -27,6 +28,6 @@ module example1(x1, x2, s, f);
 	and(g, k, x1);
 	and(h, s, x2);
 	or(f, g, h);
-endmodule
-	
-```
\ No newline at end of file
+endmodule	
+```
+