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education/computer engineering/ECE2700/Verilog.md
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@ -19,6 +19,7 @@
- Originally intended for simulation of logic networks, later adapted to synthesis - Originally intended for simulation of logic networks, later adapted to synthesis
```verilog ```verilog
//
module example1(x1, x2, s, f); module example1(x1, x2, s, f);
input x1, x2, s; input x1, x2, s;
output f; output f;
@ -27,6 +28,6 @@ module example1(x1, x2, s, f);
and(g, k, x1); and(g, k, x1);
and(h, s, x2); and(h, s, x2);
or(f, g, h); or(f, g, h);
endmodule endmodule
```
```