From 46f7a2c9b5d6ffae70970146a6c2dd8006f02736 Mon Sep 17 00:00:00 2001 From: arc Date: Mon, 27 Jan 2025 10:47:59 -0700 Subject: [PATCH] vault backup: 2025-01-27 10:47:59 --- education/computer engineering/ECE2700/Verilog.md | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/education/computer engineering/ECE2700/Verilog.md b/education/computer engineering/ECE2700/Verilog.md index 4320573..4aed32a 100644 --- a/education/computer engineering/ECE2700/Verilog.md +++ b/education/computer engineering/ECE2700/Verilog.md @@ -56,7 +56,4 @@ endmodule - Initialize Inputs - Wait - Test every possible combination of inputs and validate that the outputs are correct - -- $\$display("Hello, world)$ - - +- Debug output can be displayed with `$display("Hello world");`