diff --git a/education/computer engineering/ECE2700/Verilog.md b/education/computer engineering/ECE2700/Verilog.md
index 4320573..4aed32a 100644
--- a/education/computer engineering/ECE2700/Verilog.md	
+++ b/education/computer engineering/ECE2700/Verilog.md	
@@ -56,7 +56,4 @@ endmodule
 - Initialize Inputs
 - Wait
 - Test every possible combination of inputs and validate that the outputs are correct
-
-- $\$display("Hello, world)$ 
-
-
+- Debug output can be displayed with `$display("Hello world");`