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education/computer engineering/ECE2700/Verilog.md
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@ -19,11 +19,14 @@
- Originally intended for simulation of logic networks, later adapted to synthesis - Originally intended for simulation of logic networks, later adapted to synthesis
```verilog ```verilog
// // V---V---v--v-----portlist (not ordered)
module example1(x1, x2, s, f); module example1(x1, x2, s, f);
// Defining the types of the various ports
input x1, x2, s; input x1, x2, s;
output f; output f;
// The first argument is the output value.
// In this example, `k`, `g`, `h`, `f` are implicitly declared.
// They could also be declared manually with the syntax `wire foo`, alongside the `input` and `output` declarations
not(k, s); not(k, s);
and(g, k, x1); and(g, k, x1);
and(h, s, x2); and(h, s, x2);