From 0784d7df66e6a5990cea0995e87200574dc15121 Mon Sep 17 00:00:00 2001 From: arc Date: Fri, 17 Jan 2025 16:01:27 -0700 Subject: [PATCH] vault backup: 2025-01-17 16:01:27 --- education/computer engineering/ECE2700/Verilog.md | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/education/computer engineering/ECE2700/Verilog.md b/education/computer engineering/ECE2700/Verilog.md index 11089df..c69061f 100644 --- a/education/computer engineering/ECE2700/Verilog.md +++ b/education/computer engineering/ECE2700/Verilog.md @@ -19,11 +19,14 @@ - Originally intended for simulation of logic networks, later adapted to synthesis ```verilog -// +// V---V---v--v-----portlist (not ordered) module example1(x1, x2, s, f); + // Defining the types of the various ports input x1, x2, s; output f; - + // The first argument is the output value. + // In this example, `k`, `g`, `h`, `f` are implicitly declared. + // They could also be declared manually with the syntax `wire foo`, alongside the `input` and `output` declarations not(k, s); and(g, k, x1); and(h, s, x2);