58 lines
1.7 KiB
Markdown
58 lines
1.7 KiB
Markdown
## Boolean Engineering
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- Truth tables
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- Only practical for small circuits
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- Schematic capture
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- Using CAD to place logic gates on a virtual canvas
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- Facilitates *hierarchical design*
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- Good for larger circuits
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- Don't scale well for very large circuits
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- Hardware Description Languages
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- Enables hierarchical design
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- Standardized by IEEE
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- Design is more portable
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- Usable in combination with schematic design
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# Verilog
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- Originally developed by Gateway Design Automation
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- Put in public domain in 1990
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- Standardized in 1995
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- Originally intended for simulation of logic networks, later adapted to synthesis
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- Behavioral Verilog describes broader behavior, at a higher level
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```verilog
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// V---V---v--v-----portlist (not ordered)
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module example1(x1, x2, s, f);
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// Defining the types of the various ports
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input x1, x2, s;
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output f;
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// The first argument is the output value.
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// In this example, `k`, `g`, `h`, `f` are implicitly declared.
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// They could also be declared manually with the syntax `wire foo`, alongside the `input` and `output` declarations
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not(k, s); // You can also NOT a variable using a tilde, eg `~s`
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and(g, k, x1);
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and(h, s, x2);
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or(f, g, h);
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endmodule
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```
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```verilog
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// V---V---v--v-----portlist (not ordered)
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module example1(x1, x2, s, f);
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// Defining the types of the various ports
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input x1, x2, s;
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output f;
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// You can also do this
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assign f = (~s & x1) | (s & x2);
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// Or this
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always @(a, b)
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// always @(....) says "do this stuff whenever any of the values inside of @(...) change"
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{s1, s0} = a + b;
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endmodule
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```
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- Structural Verilog describes how things are laid out at a logic level
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## Testbench Layout
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