diff --git a/education/computer engineering/ECE2700/Verilog.md b/education/computer engineering/ECE2700/Verilog.md
index 3f221b5..5eb115f 100644
--- a/education/computer engineering/ECE2700/Verilog.md	
+++ b/education/computer engineering/ECE2700/Verilog.md	
@@ -18,6 +18,7 @@
 - Standardized in 1995
 - Originally intended for simulation of logic networks, later adapted to synthesis
 
+- Behavioral Verilog describes broader behavior, at a higher level
 ```verilog
 //              V---V---v--v-----portlist (not ordered)
 module example1(x1, x2, s, f);
@@ -34,6 +35,23 @@ module example1(x1, x2, s, f);
 endmodule	
 ```
 
-- Behavioral Verilog describes broader behavior, at a higher level
+```verilog
+//              V---V---v--v-----portlist (not ordered)
+module example1(x1, x2, s, f);
+	// Defining the types of the various ports
+	input x1, x2, s;
+	output f;
+	// You can also do this
+	assign f = (~s & x1) | (s & x2);
+	// Or this
+	always @(a, b)
+	// always @(....) says "do this stuff whenever any of the values inside of @(...) change"
+		{s1, s0} = a + b;
+endmodule	
+```
 - Structural Verilog describes how things are laid out at a logic level
 
+## Testbench Layout
+
+
+