From b30345915fa4d33d2f3faacbde3000a740993a06 Mon Sep 17 00:00:00 2001 From: arc Date: Fri, 17 Jan 2025 14:58:02 -0700 Subject: [PATCH] vault backup: 2025-01-17 14:58:02 --- education/computer engineering/ECE2700/Verilog.md | 15 +++++++++++++++ education/math/MATH1050/Systems of Equations.md | 1 + 2 files changed, 16 insertions(+) create mode 100644 education/computer engineering/ECE2700/Verilog.md diff --git a/education/computer engineering/ECE2700/Verilog.md b/education/computer engineering/ECE2700/Verilog.md new file mode 100644 index 0000000..a84a83a --- /dev/null +++ b/education/computer engineering/ECE2700/Verilog.md @@ -0,0 +1,15 @@ +## Boolean Engineering +- Truth tables + - Only practical for small circuits +- Schematic capture + - Using CAD to place logic gates on a virtual canvas + - Facilitates *hierarchical design* + - Good for larger circuits + - Don't scale well for very large circuits +- Hardware Description Languages + - Enables hierarchical design + - Standardized by IEEE + - Design is more portable + - Usable in combination with schematic design + +# Verilog diff --git a/education/math/MATH1050/Systems of Equations.md b/education/math/MATH1050/Systems of Equations.md index f9643bd..93c5585 100644 --- a/education/math/MATH1050/Systems of Equations.md +++ b/education/math/MATH1050/Systems of Equations.md @@ -4,6 +4,7 @@ | Inconsistent | Parallel lines, no solution | | Independent | The lines only cross at one point. | | Dependant | The lines are identical, and there are infinitely many solutions. Both equations represent the same line when plotted. | + # Solving ## Graphing Graph the two equations, and look for points where they intersect