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education/computer engineering/ECE2700/Verilog.md
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@ -21,5 +21,12 @@
```verilog ```verilog
module example1(x1, x2, s, f); module example1(x1, x2, s, f);
input x1, x2, s; input x1, x2, s;
output f;
not(k, s);
and(g, k, x1);
and(h, s, x2);
or(f, g, h);
endmodule
``` ```