From 77ec466cd0681d78dbd2036dfe7b82ff3a1c556e Mon Sep 17 00:00:00 2001 From: arc Date: Fri, 17 Jan 2025 15:51:27 -0700 Subject: [PATCH] vault backup: 2025-01-17 15:51:27 --- education/computer engineering/ECE2700/Verilog.md | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/education/computer engineering/ECE2700/Verilog.md b/education/computer engineering/ECE2700/Verilog.md index 15fa03c..f356e82 100644 --- a/education/computer engineering/ECE2700/Verilog.md +++ b/education/computer engineering/ECE2700/Verilog.md @@ -21,5 +21,12 @@ ```verilog module example1(x1, x2, s, f); input x1, x2, s; + output f; + + not(k, s); + and(g, k, x1); + and(h, s, x2); + or(f, g, h); +endmodule ``` \ No newline at end of file