diff --git a/education/computer engineering/ECE2700/Verilog.md b/education/computer engineering/ECE2700/Verilog.md
index 15fa03c..f356e82 100644
--- a/education/computer engineering/ECE2700/Verilog.md	
+++ b/education/computer engineering/ECE2700/Verilog.md	
@@ -21,5 +21,12 @@
 ```verilog
 module example1(x1, x2, s, f);
 	input x1, x2, s;
+	output f;
+
+	not(k, s);
+	and(g, k, x1);
+	and(h, s, x2);
+	or(f, g, h);
+endmodule
 	
 ```
\ No newline at end of file