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education/computer engineering/ECE2700/Verilog/Modules.md

@@ -86,3 +86,28 @@ endmodule
 ```
 
 # Instantiation
+Larger designs can be built by using multiple smaller modules.
+
+Modules can be *instantiated* within other modules and ports, and these *instances* can be connected with other signals.
+
+These port connections can be defined by an *ordered list*, or by *name*.
+
+### By Ordered List
+```verilog
+module submodule (input x, y, z, output o);
+	// ------- snip -------
+endmodule
+
+module parent;
+	wire a, b, c;
+	wire o;
+	// Similar to C, the type of the module is first, followed by
+	// the name of the module instance.
+	submodule foo (a, b, c, o);
+	
+```
+
+### By Name
+Ports can also be joined by explicitly defining the name.
+
+Syntactically, this is done with a dot (`.`), followed by the port name defined by the design, followed by the signal name to connect, wrapped in paranethesis (`.)