From 2456b82189717d64fa7af9709ec6c954c334d4db Mon Sep 17 00:00:00 2001 From: arc Date: Mon, 3 Feb 2025 11:34:23 -0700 Subject: [PATCH] vault backup: 2025-02-03 11:34:23 --- .../ECE2700/Verilog/Modules.md | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/education/computer engineering/ECE2700/Verilog/Modules.md b/education/computer engineering/ECE2700/Verilog/Modules.md index ea7c1bf..f64331f 100644 --- a/education/computer engineering/ECE2700/Verilog/Modules.md +++ b/education/computer engineering/ECE2700/Verilog/Modules.md @@ -86,3 +86,28 @@ endmodule ``` # Instantiation +Larger designs can be built by using multiple smaller modules. + +Modules can be *instantiated* within other modules and ports, and these *instances* can be connected with other signals. + +These port connections can be defined by an *ordered list*, or by *name*. + +### By Ordered List +```verilog +module submodule (input x, y, z, output o); + // ------- snip ------- +endmodule + +module parent; + wire a, b, c; + wire o; + // Similar to C, the type of the module is first, followed by + // the name of the module instance. + submodule foo (a, b, c, o); + +``` + +### By Name +Ports can also be joined by explicitly defining the name. + +Syntactically, this is done with a dot (`.`), followed by the port name defined by the design, followed by the signal name to connect, wrapped in paranethesis (`.) \ No newline at end of file