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education/computer engineering/ECE2700/Verilog.md
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@ -27,10 +27,13 @@ module example1(x1, x2, s, f);
// The first argument is the output value. // The first argument is the output value.
// In this example, `k`, `g`, `h`, `f` are implicitly declared. // In this example, `k`, `g`, `h`, `f` are implicitly declared.
// They could also be declared manually with the syntax `wire foo`, alongside the `input` and `output` declarations // They could also be declared manually with the syntax `wire foo`, alongside the `input` and `output` declarations
not(k, s); not(k, s); // You can also NOT a variable using a tilde, eg `~s`
and(g, k, x1); and(g, k, x1);
and(h, s, x2); and(h, s, x2);
or(f, g, h); or(f, g, h);
endmodule endmodule
``` ```
- Behavioral Verilog describes broader behavior, at a higher level
- Structural Verilog describes how things are laid out at a logic level