From 08dcd5104e240f1d3e3e3a6c1f9080e115c71c27 Mon Sep 17 00:00:00 2001 From: arc Date: Fri, 17 Jan 2025 16:06:27 -0700 Subject: [PATCH] vault backup: 2025-01-17 16:06:27 --- education/computer engineering/ECE2700/Verilog.md | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/education/computer engineering/ECE2700/Verilog.md b/education/computer engineering/ECE2700/Verilog.md index c69061f..3f221b5 100644 --- a/education/computer engineering/ECE2700/Verilog.md +++ b/education/computer engineering/ECE2700/Verilog.md @@ -27,10 +27,13 @@ module example1(x1, x2, s, f); // The first argument is the output value. // In this example, `k`, `g`, `h`, `f` are implicitly declared. // They could also be declared manually with the syntax `wire foo`, alongside the `input` and `output` declarations - not(k, s); + not(k, s); // You can also NOT a variable using a tilde, eg `~s` and(g, k, x1); and(h, s, x2); or(f, g, h); endmodule ``` +- Behavioral Verilog describes broader behavior, at a higher level +- Structural Verilog describes how things are laid out at a logic level +