42 lines
1.1 KiB
Markdown
42 lines
1.1 KiB
Markdown
# Feb 3, 2025 | ECE2700; HW 2 | Boehme, James
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# 1.
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## Problem Statement:
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> Describe in Verilog, a full adder that accepts the following three one bit inputs: $x$, $y$, and the carry-in bit $c$; and it generates the following two one-bit outputs: the sum bit $sum$ and the carry-out bit $cout$.
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> **Part a)** For the first full-adder design, describe the $sum$ output using *structural* verilog, and the carry-out output $cout$ using behavioral verilog.
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> **Part B)** Describe the second full-adder design using *hierarchical* Verilog. Describe the half-adder module first using *behavioral Verilog*. Then instantiate two half adders in your full adder.
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> **Part C)** Create a Verilog testbench for the complete full-adder circuit. Make sure your testbench provides all input combinations for your full adder module.
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## Given
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The logic expressions
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$$ sum = \bar{x}y\bar{c}_i + x\bar{y}\bar{c}_i +\bar{x}\bar{y}\bar{c}_i + xyc_i $$
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$$ cout = xy + xc_i + yc_i $$
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## Find
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# <u>Solution:</u>
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## a)
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## b)
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## c)
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# 2.
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## Problem Statement
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## Given
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## Find
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# <u>Solution</u>
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