51 lines
1.8 KiB
Markdown
51 lines
1.8 KiB
Markdown
- Output depends on input and past behavior
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- Requires use of storage elements
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# Latches
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## SR Latch
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SR stands for *Set*/*Reset*, and functions like so:
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- When a signal comes into $S$, $Q_a$ is **set** on and stays on until a signal comes into $R$, at which point the output ($Q_a$) is **reset**, back to zero.
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- $S$ and $R$ are interchangeable, it just impacts whether $Q_a$ or $Q_b$ is set/reset.
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Truth table:
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| $S$ | $R$ | $Q_a$ | $Q_b$ |
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| --- | --- | ----- | ----- |
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| 0 | 0 | 0/1 | 1/0 |
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| 0 | 1 | 0 | 1 |
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| 1 | 0 | 1 | 0 |
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| 1 | 1 | 0 | 0 |
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![[Pasted image 20250303095542.png]]
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## Gated Latch
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A gated latch is similar to a basic latch, but the output only changes when $clk = 1$.
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## D Latch
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A D latch has two inputs, $clk$ and $data$. When $clk$ is high, $data$ is stored.
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# Flip Flops
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A latch, but the output only changes on one of the clock edges
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- Can be a rising edge latch or a falling edge latch
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## JK Flip Flop
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Similar to an SR flip flop, a JK flip flop has set/reset inputs, but when *both* inputs are high, then the output is toggled.
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## T Flip Flop
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A T Flip Flip, or a toggle flip flop has two inputs:
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- $clk$ - Clock input
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- $T$ - Whenever $T$ goes from low to high, the output toggles its state
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# Registers
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## Shift Register
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![[Pasted image 20250317101146.png]]
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Above is a simple shift register.
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## Parallel Shift Register
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A parallel shift register has 4 inputs, 4 outputs, a serial input, and a shift/load input.
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When the *load* input is high, the input is stored into the register. When the *shift* input is high, the registers are shifted and the serial input is read into the new space.
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# Counters
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## A 3-bit Up-counter
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![[Pasted image 20250317102911.png]]
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# Synchronous Sequential Circuits
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- A synchronous circuit is clock driven, while an asynchronous circuit is not.
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