88 lines
2.8 KiB
Markdown
88 lines
2.8 KiB
Markdown
There are two main categories of data types in Verilog. These categories differ in the underlying hardware structure they represent, and they differ in the way they are assigned and retain values.
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# Nets
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A *net* refers to a *network* of connections that join two or more devices together.
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Nets connect different hardware entities and *do not store values*.
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## Wire
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A `wire` is the most commonly used type of net. When a port is declared in Verilog, it is implicitly given a type of `wire`.
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It is illegal to re-declare a name already in use by a net:
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```verilog
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module foo;
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wire abc;
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wire a;
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wire b;
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wire c;
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wire abc; // ILLEGAL: The wire `abc` is already defined
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```
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# Variables
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A variable is a data storage element. They retain the last input given.
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```verilog
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```verilog
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module testbench;
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integer int_a; // Integer variable
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real real_b; // Real variable
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time time_c; // Time variable
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initial begin
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int_a = 32'hfacd_1b34; // Assign an integer value
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real_b = 0.1234567; // Assign a floating point value
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#20; // Advance simulation time by 20 units
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time_c = $time; // Assign current simulation time
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// Now print all variables using $display system task
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$display ("int_a = 0x%0h", int_a);
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$display ("real_b = %0.5f", real_b);
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$display ("time_c = %0t", time_c);
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end
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endmodule
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```
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```
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## Registers
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A `reg` can be used to model hardware registers because it stores a value until the next assignment.
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### Integer
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A Verilog `integer` type is a 32 bit wide storage value. It does not *need* to store integers, it can be used for other purposes.
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```verilog
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integer count;
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```
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### Time
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A `time` variable is unsigned, 64 bits wide, and can be used to store time duration for debugging purposes. `realtime` is similar, but time is stored as a floating bit value.
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## Real
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The `real` type denotes a floating point value.
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## Strings
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Strings are stored in a vector of `reg`s. The width of the `reg` *must* be large enough to hold the string.
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Each character in a string represents a one byte ASCII value. If the size of the variable is smaller than the string, the string is truncated.
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# Scalar and Vector Types
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By default, declarations of a net or `reg` value is 1 bit wide, referred to as a *scalar* value (only a single value).
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```verilog
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// Scalar declaration
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wire foo;
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// Vector declaration, with 8 bits.
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wire [7:0] bar;
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```
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Individual bits in a vector can be accessed using array operators, eg `[i]`.
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```verilog
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reg [7:0] foo;
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// Write to bit 0
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foo [0] = 1;
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```
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## Part selects
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A range of contiguous bits from within another vector can be selected, referred to as a part select. This range can then be treated as a vector.
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```verilog
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reg [31:0] foo;
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// Select bits 23 through 16 (inclusive), and assign the 8 bit hex value `0xff` to them.
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foo [23:16] = 8'hff;
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``` |