113 lines
2.8 KiB
Markdown
113 lines
2.8 KiB
Markdown
Modules are the building block through which Verilog is built.
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Each module can be thought of as a black box with a series of inputs, and a series of outputs. Changing the input changes the outputs.
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Module definitions are started with the `module` keyword, and closed with the `endmodule` keyword.
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## Syntax
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The general syntax of a module is as follows:
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```verilog
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module <name> ([port_list]);
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// Contents of the module
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endmodule
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// The port list is optional
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module <name>;
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// Contents
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endmodule
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```
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Below is an example of the structure of a half adder module:
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```verilog
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module half_adder(
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input a,
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input b,
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output sum_bit,
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output carry_bit
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);
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// ------- snip ------------
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endmodule
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```
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## Ports
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Ports are a set of signals that act as input and outputs for a particular module.
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There are 3 kinds of ports:
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- `input`: Input ports can only receive values from the outside. `input` ports cannot be written to.
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- `output`: Output ports can be written to, but not read from.
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- `inout`: Inout ports can send *and* receive values.
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Ports can be declared in the port list, or in the module body. Ports declared in the port list can optionally omit their type and only declare a name, to be specified within the body of the module:
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```verilog
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module half_adder(
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a,
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b,
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sum_bit,
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carry_bit
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);
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input a;
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input b;
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output sum_bit;
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output carry_bit;
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// ----------- snip -----------
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endmodule
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```
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The full type of a port can also be defined within the portlist:
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```verilog
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```verilog
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module half_adder(
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input wire a,
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input wire b,
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output wire sum_bit,
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output wire carry_bit
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);
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input a;
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input b;
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output sum_bit;
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output carry_bit;
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// ----------- snip -----------
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endmodule
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```
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### Port types
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If no type is defined, ports are implicitly defined as *nets* of type `wire`.
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> In verilog, the term *net* refers to network, and it refers to a connection that joins two or more devices together.
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Ports can be a vector type:
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```verilog
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module test(a, b, c);
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input [7:0] a;
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input [7:0] b;
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output [7:0] c;
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// -------- snip ---------
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endmodule
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```
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# Instantiation
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Larger designs can be built by using multiple smaller modules.
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Modules can be *instantiated* within other modules and ports, and these *instances* can be connected with other signals.
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These port connections can be defined by an *ordered list*, or by *name*.
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### By Ordered List
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```verilog
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module submodule (input x, y, z, output o);
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// ------- snip -------
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endmodule
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module parent;
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wire a, b, c;
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wire o;
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// Similar to C, the type of the module is first, followed by
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// the name of the module instance.
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submodule foo (a, b, c, o);
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```
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### By Name
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Ports can also be joined by explicitly defining the name.
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Syntactically, this is done with a dot (`.`), followed by the port name defined by the design, followed by the signal name to connect, wrapped in paranethesis (`.) |