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education/computer engineering/ECE2700/Verilog/Verilog.md

@@ -17,8 +17,11 @@
 - Put in public domain in 1990
 - Standardized in 1995
 - Originally intended for simulation of logic networks, later adapted to synthesis
+- Structural Verilog describes how things are laid out at a logic level.
 
-- Behavioral Verilog describes broader behavior, at a higher level
+## Structural Verilog
+Structural Verilog describes things at a logic level.
+- The use of logic gates and continuous assignment are markers of structural Verilog.
 ```verilog
 //              V---V---v--v-----portlist (not ordered)
 module example1(x1, x2, s, f);
@@ -36,9 +39,9 @@ module example1(x1, x2, s, f);
 	assign f = (~s & x1) | (s & x2);
 endmodule	
 ```
-
-- Structural Verilog describes how things are laid out at a logic level.
-- 
+## Behavioral Verilog
+Behavioral Verilog describes broader behavior, at a higher level
+- The use of `reg`s, time delays, arithmetic expressions, procedural assignment, and other control flow constructs are markers of behavioral Verilog.
 ```verilog
 //              V---V---v--v-----portlist (not ordered)
 module example1(x1, x2, s, f);