From ff4330471b19bc5d2c4126dd2db8d53dc2914106 Mon Sep 17 00:00:00 2001 From: arc Date: Mon, 3 Feb 2025 17:23:29 -0700 Subject: [PATCH] vault backup: 2025-02-03 17:23:28 --- .../computer engineering/ECE2700/Verilog/Verilog.md | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/education/computer engineering/ECE2700/Verilog/Verilog.md b/education/computer engineering/ECE2700/Verilog/Verilog.md index a14ea62..e95ca8c 100644 --- a/education/computer engineering/ECE2700/Verilog/Verilog.md +++ b/education/computer engineering/ECE2700/Verilog/Verilog.md @@ -17,8 +17,11 @@ - Put in public domain in 1990 - Standardized in 1995 - Originally intended for simulation of logic networks, later adapted to synthesis +- Structural Verilog describes how things are laid out at a logic level. -- Behavioral Verilog describes broader behavior, at a higher level +## Structural Verilog +Structural Verilog describes things at a logic level. +- The use of logic gates and continuous assignment are markers of structural Verilog. ```verilog // V---V---v--v-----portlist (not ordered) module example1(x1, x2, s, f); @@ -36,9 +39,9 @@ module example1(x1, x2, s, f); assign f = (~s & x1) | (s & x2); endmodule ``` - -- Structural Verilog describes how things are laid out at a logic level. -- +## Behavioral Verilog +Behavioral Verilog describes broader behavior, at a higher level +- The use of `reg`s, time delays, arithmetic expressions, procedural assignment, and other control flow constructs are markers of behavioral Verilog. ```verilog // V---V---v--v-----portlist (not ordered) module example1(x1, x2, s, f);