vault backup: 2025-02-03 11:39:23

education/computer engineering/ECE2700/Verilog/Modules.md

@@ -104,10 +104,30 @@ module parent;
 	// Similar to C, the type of the module is first, followed by
 	// the name of the module instance.
 	submodule foo (a, b, c, o);
-	
+endmodule
 ```
 
 ### By Name
 Ports can also be joined by explicitly defining the name.
 
-Syntactically, this is done with a dot (`.`), followed by the port name defined by the design, followed by the signal name to connect, wrapped in paranethesis (`.)
+Syntactically, this is done with a dot (`.`), followed by the port name defined by the design, followed by the signal name to connect, wrapped in parenthesis (`.x(a)`).
+```verilog
+module submodule (input x, y, z, output o);
+	// ------------snip-----------------
+endmodule
+
+module parent;
+	wire a, b, c;
+	wire o;
+	submodule foo (
+		.x(a),
+		.y(b),
+		.z(c),
+		.o(o)
+	);
+```
+
+Because association is done by name, the order of definition does not matter.
+
+### Unconnected ports
+Ports that are not connected to any wire by the parent module will have a value of high impedance