From b4c30e79efa1575fab6a72e3e97e5f3c994bfad9 Mon Sep 17 00:00:00 2001 From: arc Date: Mon, 3 Feb 2025 11:39:23 -0700 Subject: [PATCH] vault backup: 2025-02-03 11:39:23 --- .../ECE2700/Verilog/Modules.md | 24 +++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/education/computer engineering/ECE2700/Verilog/Modules.md b/education/computer engineering/ECE2700/Verilog/Modules.md index f64331f..dfacc87 100644 --- a/education/computer engineering/ECE2700/Verilog/Modules.md +++ b/education/computer engineering/ECE2700/Verilog/Modules.md @@ -104,10 +104,30 @@ module parent; // Similar to C, the type of the module is first, followed by // the name of the module instance. submodule foo (a, b, c, o); - +endmodule ``` ### By Name Ports can also be joined by explicitly defining the name. -Syntactically, this is done with a dot (`.`), followed by the port name defined by the design, followed by the signal name to connect, wrapped in paranethesis (`.) \ No newline at end of file +Syntactically, this is done with a dot (`.`), followed by the port name defined by the design, followed by the signal name to connect, wrapped in parenthesis (`.x(a)`). +```verilog +module submodule (input x, y, z, output o); + // ------------snip----------------- +endmodule + +module parent; + wire a, b, c; + wire o; + submodule foo ( + .x(a), + .y(b), + .z(c), + .o(o) + ); +``` + +Because association is done by name, the order of definition does not matter. + +### Unconnected ports +Ports that are not connected to any wire by the parent module will have a value of high impedance \ No newline at end of file