vault backup: 2025-02-03 13:18:54

education/computer engineering/ECE2700/Homework/Homework 2.md

@@ -4,12 +4,27 @@
 ## Problem Statement:
 > Describe in Verilog, a full adder that accepts the following three one bit inputs: $x$, $y$, and the carry-in bit $c$; and it generates the following two one-bit outputs: the sum bit $sum$ and the carry-out bit $cout$. 
 
-> Part a) For the first full-adder design, describe the $sum$ output using 
+> **Part a)** For the first full-adder design, describe the $sum$ output using *structural* verilog, and the carry-out output $cout$ using behavioral verilog.
+
+> **Part B)** Describe the second full-adder design using *hierarchical* Verilog. Describe the half-adder module first using *behavioral Verilog*. Then instantiate two half adders in your full adder.
+
+> **Part C)** Create a Verilog testbench for the complete full-adder circuit. Make sure your testbench provides all input combinations for your full adder module.
+
 ## Given
+The logic expressions
+$$ sum = \bar{x}y\bar{c}_i + x\bar{y}\bar{c}_i +\bar{x}\bar{y}\bar{c}_i + xyc_i $$
+$$ cout = xy + xc_i + yc_i $$
 ## Find
 
 ---
 # <u>Solution:</u>
+## A
+---
+---
+# 2.
+## Problem Statement
 
+## Given
+## Find
 ---
 ---