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education/computer engineering/ECE2700/Verilog/Modules.md
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@ -7,6 +7,7 @@ Module definitions are started with the `module` keyword, and closed with the `e
## Syntax
The general syntax of a module is as follows:
```verilog
// This line is referred to as the *module header*
module <name> ([port_list]);
// Contents of the module
endmodule
@ -130,4 +131,5 @@ module parent;
Because association is done by name, the order of definition does not matter.
### Unconnected ports
Ports that are not connected to any wire by the parent module will have a value of high impedance
Ports that are not connected to any wire by the parent module will have a value of high impedance, and is considered unknown/undefined.