From 3b4bb73264e95fcb3ad64a8fe8fc5436a76bcac1 Mon Sep 17 00:00:00 2001 From: arc Date: Mon, 3 Feb 2025 11:44:23 -0700 Subject: [PATCH] vault backup: 2025-02-03 11:44:23 --- education/computer engineering/ECE2700/Verilog/Modules.md | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/education/computer engineering/ECE2700/Verilog/Modules.md b/education/computer engineering/ECE2700/Verilog/Modules.md index dfacc87..8444216 100644 --- a/education/computer engineering/ECE2700/Verilog/Modules.md +++ b/education/computer engineering/ECE2700/Verilog/Modules.md @@ -7,6 +7,7 @@ Module definitions are started with the `module` keyword, and closed with the `e ## Syntax The general syntax of a module is as follows: ```verilog +// This line is referred to as the *module header* module ([port_list]); // Contents of the module endmodule @@ -130,4 +131,5 @@ module parent; Because association is done by name, the order of definition does not matter. ### Unconnected ports -Ports that are not connected to any wire by the parent module will have a value of high impedance \ No newline at end of file +Ports that are not connected to any wire by the parent module will have a value of high impedance, and is considered unknown/undefined. +