arc/notes
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

vault backup: 2025-02-03 11:44:23

Browse Source
This commit is contained in:
arc 2025-02-03 11:44:23 -07:00
parent b4c30e79ef
commit 3b4bb73264
1 changed files with 3 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
education/computer engineering/ECE2700/Verilog/Modules.md
View File

@ -7,6 +7,7 @@ Module definitions are started with the `module` keyword, and closed with the `e
## Syntax ## Syntax
The general syntax of a module is as follows: The general syntax of a module is as follows:
```verilog ```verilog
// This line is referred to as the *module header*
module <name> ([port_list]); module <name> ([port_list]);
// Contents of the module // Contents of the module
endmodule endmodule
@ -130,4 +131,5 @@ module parent;
Because association is done by name, the order of definition does not matter. Because association is done by name, the order of definition does not matter.
### Unconnected ports ### Unconnected ports
Ports that are not connected to any wire by the parent module will have a value of high impedance Ports that are not connected to any wire by the parent module will have a value of high impedance, and is considered unknown/undefined.