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education/computer engineering/ECE2700/Verilog/Types.md

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-There are two main categories of data types in Verilog. These ty
+There are two main categories of data types in Verilog. These categories differ in the underlying hardware structure they represent, and they differ in the way they are assigned and retain values.
 # Nets
+A *net* refers to a *network* of connections that join two or more devices together.
+
+Nets connect different hardware entities and *do not store values*. 
+## Wire
+A `wire` is the most commonly used type of net. When a port is declared in Verilog, it is implicitly given a type of `wire`.
+
+It is illegal to re-declare a name already in use by a net
+# Scalar and Vector