From 02954021316615045f72c9601fd7d3b26b379ec0 Mon Sep 17 00:00:00 2001 From: arc Date: Mon, 3 Feb 2025 10:09:19 -0700 Subject: [PATCH] vault backup: 2025-02-03 10:09:19 --- .../computer engineering/ECE2700/Verilog/Types.md | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/education/computer engineering/ECE2700/Verilog/Types.md b/education/computer engineering/ECE2700/Verilog/Types.md index 2244096..92db35a 100644 --- a/education/computer engineering/ECE2700/Verilog/Types.md +++ b/education/computer engineering/ECE2700/Verilog/Types.md @@ -1,2 +1,10 @@ -There are two main categories of data types in Verilog. These ty +There are two main categories of data types in Verilog. These categories differ in the underlying hardware structure they represent, and they differ in the way they are assigned and retain values. # Nets +A *net* refers to a *network* of connections that join two or more devices together. + +Nets connect different hardware entities and *do not store values*. +## Wire +A `wire` is the most commonly used type of net. When a port is declared in Verilog, it is implicitly given a type of `wire`. + +It is illegal to re-declare a name already in use by a net +# Scalar and Vector