14 lines
438 B
Markdown
14 lines
438 B
Markdown
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Modules are the building block through which Verilog is built.
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Each module can be thought of as a black box with a series of inputs, and a series of outputs. Changing the input changes the outputs.
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Module definitions are started with the `module` keyword, and closed with the `endmodule` keyword.
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The general syntax of a module is as follows:
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```verilog
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module <name> ([port_list]);
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// Contents of the module
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endmodule
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// The por
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```
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