Modules are the building block through which Verilog is built.

Each module can be thought of as a black box with a series of inputs, and a series of outputs. Changing the input changes the outputs.

Module definitions are started with the `module` keyword, and closed with the `endmodule` keyword.

The general syntax of a module is as follows:
```verilog
module <name> ([port_list]);
	// Contents of the module
endmodule

// The por
```