Modules are the building block through which Verilog is built.

Each module can be thought of as a black box with a series of inputs, and a series of outputs. Changing the input changes the outputs.

Module definitions are started with the `module` keyword, and closed with the `endmodule` keyword.

## Syntax
The general syntax of a module is as follows:
```verilog
module <name> ([port_list]);
	// Contents of the module
endmodule

// The port list is optional
module <name>;
	// Contents
endmodule
```

Below is an example of the structure of a half adder module:
```verilog
module half_adder(
	input a,
	input b,
	output sum_bit,
	output carry_bit
	);
	// ------- snip ------------
endmodule
```

## Ports
Ports are a set of signals that act as input and outputs for a particular module. 

There are 3 kinds of ports:
- `input`: Input ports can only receive values from the outside. `input` ports cannot be written to.
- `output`: Output ports can be written to, but not read from.
- `inout`: Inout ports can send *and* receive values.

Ports can be declared in the port list, or in the module body. Ports declared in the port list can optionally omit their type, to be specified within the body of the module:
```verilog
module half_adder(
	a,
	b,
	sum_bit,
	carry_bit
	);
	input a;
	input b;
	output sum_bit;
	output carry_bit;
endmodule
```

### Port types
If no type is defined, ports are implicitly defined as *nets* of type `wire`.

> In verilog, the term *net* refers to network, and it refers to a connection that joins two or more devices together.

Ports can be a vector type:
```verilog
module test(a, b, c);
		
endmodule
```