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@ -1,27 +0,0 @@
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@ -24,9 +24,7 @@ $$ V(D) = d_{n-1} * 10^{n-1} + d_{n - 2} * 10^{n-2} + \cdots + d_1 * 10^1 + d_0
In a binary or base 2 number system, each digit can be a zero or one, called a *bit*.
$$ D = d_{n-1}d_{n-2} \cdots d_1 d_0 $$
To determine the integer value, a very similar formula can be used.
$$ V(B) = b_{n-1} * 2^{n-1} + b_{n-2} * 2^{n-2} \cdots b_{1} * 2^1 + b_0 * 2^0 $$This formula can be generalized as:
*For radix $r$*:
$$ k = k_{n-1} k_{n-2} \cdots k_1 k_0$$
$$ V(B) = b_{n-1} * 2^{n-1} + b_{n-2} * 2^{n-2} \cdots b_{1} * 2^1 + b_0 * 2^0 $$
- The base of a number is often notated in the format of $(n)_b$, EG a base 10 number might be $(14)_{10}$, and a binary number might be $(10)_2$.
- The *least significant bit* (LSB) is usually the right-most bit. The highest value bit, or the *most significant bit* (MSB).
- A nibble is 4 bits, and a byte is 8 bits
@ -36,18 +34,18 @@ Repeatedly divide by 2, and track the remainder.
As an example, the below table shows how one might convert from $(857)_{10}$ to base 2.
| Equation | Remainder | |
| --------------- | --------- | --- |
| $857 / 2 = 428$ | $1$ | |
| $428 / 2 = 214$ | $0$ | |
| $214 / 2 = 107$ | $0$ | |
| $107 / 2 = 53$ | $1$ | |
| $53 / 2 = 26$ | $1$ | |
| $26 / 2 = 13$ | $0$ | |
| $13 / 2 = 6$ | $1$ | |
| $6 / 2 = 3$ | $0$ | |
| $3 / 2 = 1$ | $1$ | |
| $1 / 2 = 0$ | $1$ | |
| Equation | Remainder |
| --------------- | --------- |
| $857 / 2 = 428$ | $1$ |
| $428 / 2 = 214$ | $0$ |
| $214 / 2 = 107$ | $0$ |
| $107 / 2 = 53$ | $1$ |
| $53 / 2 = 26$ | $1$ |
| $26 / 2 = 13$ | $0$ |
| $13 / 2 = 6$ | $1$ |
| $6 / 2 = 3$ | $0$ |
| $3 / 2 = 1$ | $1$ |
| $1 / 2 = 0$ | $1$ |
The final answer is $1101011001$. The least significant bit is the remainder of the first division operation, and the most significant bit is the remainder of the last operation.
# Definitions

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@ -18,7 +18,6 @@
- Standardized in 1995
- Originally intended for simulation of logic networks, later adapted to synthesis
- Behavioral Verilog describes broader behavior, at a higher level
```verilog
// V---V---v--v-----portlist (not ordered)
module example1(x1, x2, s, f);
@ -35,25 +34,6 @@ module example1(x1, x2, s, f);
endmodule
```
```verilog
// V---V---v--v-----portlist (not ordered)
module example1(x1, x2, s, f);
// Defining the types of the various ports
input x1, x2, s;
output f;
// You can also do this
assign f = (~s & x1) | (s & x2);
// Or this
always @(a, b)
// always @(....) says "do this stuff whenever any of the values inside of @(...) change"
{s1, s0} = a + b;
endmodule
```
- Behavioral Verilog describes broader behavior, at a higher level
- Structural Verilog describes how things are laid out at a logic level
## Testbench Layout
- Define UUT module
- Initialize Inputs
- Wait
- Test every possible combination of inputs and validate that the outputs are correct
- Debug output can be displayed with `$display("Hello world");`

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@ -19,20 +19,3 @@ The above formula can be used to find the *derivative*. This may also be referre
A **Secant Line** connects two points on a graph.
A **Tangent Line** represents the rate of change or slope at a single point on the graph.
# Notation
Given the equation $y = f(x)$, the following are all notations used to represent the derivative of $f$ at $x$:
- $f'(x)$
- $\dfrac{d}{dx}f(x)$
- $y'$
- $\dfrac{dy}{dx}$
- $\dfrac{df}{dx}$
- "Derivative of $f$ with respect to $x$"
# Functions that are not differentiable at a given point
- Where a function is not defined
- Where a sharp turn takes place
- If the slope of the tangent line is vertical
# Higher Order Differentials
- Take the differential of a differential