diff --git a/education/computer engineering/ECE2700/Verilog/Types.md b/education/computer engineering/ECE2700/Verilog/Types.md
index 92db35a..e9820ce 100644
--- a/education/computer engineering/ECE2700/Verilog/Types.md	
+++ b/education/computer engineering/ECE2700/Verilog/Types.md	
@@ -6,5 +6,18 @@ Nets connect different hardware entities and *do not store values*.
 ## Wire
 A `wire` is the most commonly used type of net. When a port is declared in Verilog, it is implicitly given a type of `wire`.
 
-It is illegal to re-declare a name already in use by a net
-# Scalar and Vector
+It is illegal to re-declare a name already in use by a net:
+```verilog
+module foo;
+	wire abc;
+	wire a;
+	wire b;
+	wire c;
+
+	wire abc; // ILLEGAL: The wire `abc` is already defined
+
+```
+
+# Variables
+A variable is a data storage element. They retain the last impu
+# Scalar and Vector Types