From d697cba7bad1c4591f843b4104af44a0a1a007e3 Mon Sep 17 00:00:00 2001 From: arc Date: Mon, 3 Feb 2025 09:54:19 -0700 Subject: [PATCH] vault backup: 2025-02-03 09:54:19 --- .../ECE2700/Verilog/Modules.md | 14 ++++++++++++++ .../ECE2700/{ => Verilog}/Verilog.md | 0 2 files changed, 14 insertions(+) create mode 100644 education/computer engineering/ECE2700/Verilog/Modules.md rename education/computer engineering/ECE2700/{ => Verilog}/Verilog.md (100%) diff --git a/education/computer engineering/ECE2700/Verilog/Modules.md b/education/computer engineering/ECE2700/Verilog/Modules.md new file mode 100644 index 0000000..76c233e --- /dev/null +++ b/education/computer engineering/ECE2700/Verilog/Modules.md @@ -0,0 +1,14 @@ +Modules are the building block through which Verilog is built. + +Each module can be thought of as a black box with a series of inputs, and a series of outputs. Changing the input changes the outputs. + +Module definitions are started with the `module` keyword, and closed with the `endmodule` keyword. + +The general syntax of a module is as follows: +```verilog +module ([port_list]); + // Contents of the module +endmodule + +// The por +``` \ No newline at end of file diff --git a/education/computer engineering/ECE2700/Verilog.md b/education/computer engineering/ECE2700/Verilog/Verilog.md similarity index 100% rename from education/computer engineering/ECE2700/Verilog.md rename to education/computer engineering/ECE2700/Verilog/Verilog.md