From d54cecc80147a2b1f4d2edd8eaab88b9413b4389 Mon Sep 17 00:00:00 2001
From: arc <zleyyij@users.noreply.github.com>
Date: Mon, 3 Feb 2025 09:59:19 -0700
Subject: [PATCH] vault backup: 2025-02-03 09:59:19

---
 .../ECE2700/Verilog/Modules.md                | 31 +++++++++++++++++--
 1 file changed, 29 insertions(+), 2 deletions(-)

diff --git a/education/computer engineering/ECE2700/Verilog/Modules.md b/education/computer engineering/ECE2700/Verilog/Modules.md
index 76c233e..66d89d6 100644
--- a/education/computer engineering/ECE2700/Verilog/Modules.md	
+++ b/education/computer engineering/ECE2700/Verilog/Modules.md	
@@ -4,11 +4,38 @@ Each module can be thought of as a black box with a series of inputs, and a seri
 
 Module definitions are started with the `module` keyword, and closed with the `endmodule` keyword.
 
+## Syntax
 The general syntax of a module is as follows:
 ```verilog
 module <name> ([port_list]);
 	// Contents of the module
 endmodule
 
-// The por
-```
\ No newline at end of file
+// The port list is optional
+module <name>;
+	// Contents
+endmodule
+```
+
+Below is an example of the structure of a half adder module:
+```verilog
+module half_adder(
+	input a,
+	input b
+	output sum_bit,
+	output carry_bit
+	);
+	// ------- snip ------------
+endmodule
+```
+
+## Ports
+Ports are a set of signals that act as input and outputs for a particular module. 
+
+There are 3 kinds of ports:
+- `input`: Input ports can only receive values from the outside. `input` ports cannot be written to.
+- `output`: Output ports can be written to, but not read from.
+- `inout`: Inout ports can send *and* receive values.
+
+### Port types
+If no 
\ No newline at end of file