diff --git a/education/computer engineering/ECE2700/Adders.md b/education/computer engineering/ECE2700/Adders.md
index 26e330c..2f3019f 100644
--- a/education/computer engineering/ECE2700/Adders.md	
+++ b/education/computer engineering/ECE2700/Adders.md	
@@ -1,6 +1,6 @@
 # Half Adder
 
-#
+# Full Adder
 
 # Ripple Carry Adder
 
@@ -10,4 +10,6 @@ A carry select adder is built using two ripple carry adders, and multiplexing th
 The delay is calculated like so:
 1. Given the delay of a full adder is $k$, and the delay of a 2 to 1 mux is $\frac{1}{m}k$,
 2. then the delay of a 4 bit ripple carry adder is $4k$, because it's 4 full adders chained together, running sequentially.
-3. This means that the delay of a 4 bit carry select adder is $4k + \frac{k}{m}$ 
\ No newline at end of file
+3. This means that the delay of a 4 bit carry select adder is $4k + \frac{k}{m}$ 
+
+# Carry-lookahead adder
\ No newline at end of file
diff --git a/education/computer engineering/ECE2700/Verilog/Types.md b/education/computer engineering/ECE2700/Verilog/Types.md
index d73ff0a..05d65f3 100644
--- a/education/computer engineering/ECE2700/Verilog/Types.md	
+++ b/education/computer engineering/ECE2700/Verilog/Types.md	
@@ -20,7 +20,28 @@ module foo;
 
 # Variables
 A variable is a data storage element. They retain the last input given.
+```verilog
+```verilog
+module testbench;
+  integer  	int_a; 				// Integer variable
+  real 		real_b; 			// Real variable
+  time 		time_c; 			// Time variable
 
+  initial begin
+    int_a 	= 32'hfacd_1b34; 	// Assign an integer value
+    real_b 	= 0.1234567; 		// Assign a floating point value
+
+    #20; 						// Advance simulation time by 20 units
+    time_c 	= $time; 			// Assign current simulation time
+
+    // Now print all variables using $display system task
+    $display ("int_a 	= 0x%0h", int_a);
+    $display ("real_b 	= %0.5f", real_b);
+    $display ("time_c 	= %0t", time_c);
+  end
+endmodule
+```
+```
 ## Registers
 A `reg` can be used to model hardware registers because it stores a value until the next assignment.
 
@@ -31,4 +52,9 @@ A Verilog `integer` type is a 32 bit wide storage value. It does not *need* to s
 ```
 ### Time
 A `time` variable is unsigned, 64 bits wide, and can be used to store time duration for debugging purposes. `realtime` is similar, but time is stored as a floating bit value.
+
+## Real
+The `real` type denotes a floating point value.
+
+
 # Scalar and Vector Types